1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device and, more particularly, to reduction of on-resistance of a semiconductor device, like an insulated gate transistor having a trench structure.
2. Description of the Related Art
With recent reduction of power consumption, sophistication, and speedup of electronic devices, including portable phones, semiconductor devices to be mounted in the electronic devices have also been required to pursue further reduction of power consumption and greater speedups. In order to meet the demands, transistors used in load switches, DC-DC converters, and the like, of general electronic devices have been required to exhibit smaller on-resistance. One proposed method for reducing on-resistance of a transistor is to increase the density of transistors to be placed per unit area by miniaturizing individual devices. Specifically, in relation to a vertical MOSFET including gate electrodes fabricated in respective trenches, the trenches formed in the trenches making up the transistor are arranged in a stripe pattern, to thus reduce widths of the respective trenches. Further, pitches among adjacent trenches are reduced, thereby making it possible to increase the density of the transistor.
The T-MOSFET is a MOSFET that utilizes sidewalls of respective trenches as channels by embedding gate electrodes in the respective trenches by way of a gate insulation film.
FIG. 7 (corresponding to FIG. 1 of Patent Document 1) shows a structure of a typical N-channel T-MOS. By means of epitaxial growth, an epitaxial layer 1810 is formed on a silicon substrate that is an N+-type semiconductor substrate 1800 doped with N-type impurities (of first conductivity type). The epitaxial layer 1810 includes an N-type drain region 1811, a P-type body region 1812 formed on the N-type drain region 1811, an N+-type source region 1813 formed on the body region 1812; and a P+-type body contact region 1814 that is formed so as to adjoin the source region 1813 and that is higher than the body region 1812 in terms of an impurity concentration. A trench that penetrates through the source region 1813 and the body region 1812, to thus reach an upper portion of the drain region 1811, is provided in the epitaxial layer 1810. A vertical gate electrode 1820 is embedded in the trench. A topmost surface of the vertical gate electrode 1820 is formed so as to be situated below a surface of the epitaxial layer 1810 where the source region 1813 exists. An upper area of the trench located above the vertical gate electrode 1820 is filled with an insulation film 1830. An insulating material 1840 that is to serve as a gate insulation film lies between the vertical gate electrode 1820 and walls; namely, a wall of the drain region 1811 and walls of the body region 1812 which are to act as vertical walls of the trench. Further, a common electrode 1850 connected commonly to the source region 1813 and the body contact region 1814 is formed on a surface of the epitaxial layer 1810.
In order to meet the demand for further reduction of on-resistance, miniaturization of a chip; namely, an increase in current density, and an increase in current density, various proposed techniques have been contrived to miniaturize trench pitches to a much greater extent.
FIG. 8 shows an example technique for miniaturizing a trench pitch in a T-MOS described in connection with Patent Document 2. In order to reduce the trench pitch, a width of the trench and spacing between trenches are reduced. If the width of the pitch is reduced with the structure shown in FIG. 7 being kept intact, an area of the source region 1813 and an area of the body contact region 1814 will become smaller. Consequently, contact resistance existing between a body contact electrode metal serving as the common electrode 1850 and the regions; namely, the source region 1813 and the body contact region 1814, will increase, which will pose difficulty in reducing on-resistance as targeted. In Patent Document 2, upper edges of trenches 2140 are given a “round shape” for these reasons as shown in FIG. 8. The number of trenches is reduced by increasing the length of a channel per trench (i.e., the length of a gate electrode 2120), thereby increasing spacing between the trenches and effectively increasing an area of the body contact and an area of a source contact. An increase in contact resistance, which would otherwise stem from miniaturization of the trench pitch, can be thereby prevented. Use of the technique can be said to make it possible to reduce the trench pitch from a trench pitch on the order of micrometers to a trench pitch on the order of submicrons; specifically, to a value of 1 micrometers or less.
Patent Document 1: JP-2005-32792
Patent Document 2: JP-2006-196876
However, a demand for reduction of on-resistance recently grows more than ever with further miniaturization of an element. Currently available workarounds for this demand are to merely control the resistance of the epitaxial layer 1810. For this reason, additional reduction of on-resistance has been strongly desired.
Under the circumstances, a configuration of the trench greatly affects element characteristics. In particular, contact resistance in the source contact located in the vicinity of trench openings and resistance in the source region give rise to increase in on-resistance.